To further improve the capability of information processing systems, a higher operation speed, a lower magnitude of power consumption and a higher unit capacity are required for semiconductor devices which are employed for such systems.
At present, silicon (Si) semiconductor devices are predominantly utilized for such purposes. However, since operation speed is rather limited for Si semiconductor devices due to the parameters based on the physical properties of Si, e.g., mobility of carriers moving therein, various efforts are being used to realize a higher operation speed and a lower magnitude of power consumption for semiconductor devices. One of the major aspects to which the aforementioned efforts are directed is utilization of compound semiconductors, e.g., gallium-arsenide (GaAs), in which the carrier mobility is by far greater than in Si.
Most transistors which utilize compound semiconductors are at present field effect transistors (hereinafter referred to as FET), particularly Schottky barrier gate FETs or junction gate FETs.
Since prior art semiconductor devices having a structure which allows carriers to pass through the space where impurities exist, the operation speed is rather limited due to various parameters including the effects of ionized-impurity scattering. This inspired the idea that separation of a space where carriers pass through from a space where impurities exist would be effective to increase the operation speed of a semiconductor device. Reducing this idea to practice resulted in the development of a new type of semiconductor device in which a conductive channel includes the electrons accumulated in a two-dimensional surface contiguous with a heterojunction interleaved between a pair of semiconductor layers, each having a different electron affinity. This new type of semiconductor device which utilizes the aforementioned accumulated electrons (hereinafter referred to as a two-dimensional electron gas) is named a heterojunction semiconductor device, because of the specific layer configuration. Since the thickness of a two-dimensional electron gas is extremely small, specifically, less than 100 angstroms, the two-dimensional electron gas has a geometrical position separated from either of the semiconductor layers forming the heterojunction. As a result, the two-dimensional electron gas becomes free of the effects of ionized-impurity scattering, and thus allows an extremely large amount of electron mobility, particularly at a cryogenic temperature within a temperature range not exceeding 150.degree. K.
Referring to FIGS. 1 and 2, the layer configurations of two exemplary heterojunction field effect elements will be described below.
Referring to FIG. 1, an undoped GaAs layer 2, an n-AlGaAS layer 3 and an n-type AlGaAs layer 4 are respectively grown on a semi-insulating GaAs substrate 1. Heterojunctions are formed between GaAs layer 2 and AlGaAs layer 3 and between AlGaAs layer 3 and GaAs layer 4. A gate electrode 5 is produced on AlGaAs layer 3 or in a recess from which GaAs layer 4 is selectively removed to expose AlGaAs layer 3 at this location. Source and drain electrodes 6 and 7 are produced on GaAs layer 4.
Since the n-type AlGaAs layer 3 supplies electrons to a two-dimensional electron gas 8, the n-type AlGaAs layer 3 is named an electron source layer. Gate electrode 5 functions to regulate the surface electron density of the two-dimensional electron gas 8, resultantly regulating the impedance between source electrode 6 and drain electrode 7. Thus, the heterojunction field effect element having the layer configuration shown in FIG. 1, functions as an enhancement FET.
In the case of an enhancement FET shown above, undoped GaAs layer 2 is approximately 1 .mu.m thick, n-type AlGaAs layer 3 is approximately 40 nm thick and n-type GaAs layer 4 is approximately 30 nm thick. These layers are grown in one step employing, e.g., molecular beam epitaxy (hereinafter referred to as MBE process). Impurities are introduced into the n-type AlGaAs layer 3 and n-type GaAs layer 4 during the MBE process.
A depletion type element can be produced, as shown in FIG. 2, by introducing n-type impurities or donors in the upper part of undoped GaAs layer 2 or the region where the two-dimensional electron gas 8 is otherwise accumulated, to produce an n-type region 9. In reality, however, this depletion type element does not necessarily function as a heterojunction field effect element. In other words, it rather resembles an insulated gate type FET. Since it does not necessarily show the features inherent to the aforementioned heterojunction field effect element, it can not be identified as a heterojunction field effect element.
Furthermore if an ion implantation process is employed for introduction of n-type impurities to the entire region (including a source region and a drain region) at which a depletion type element is produced (that is, an IC chip containing enhancement type elements and depletion type elements), as in the case of producing a GaAs Schottky barrier gate FET in the prior art, the problems listed below are inevitable, because a heat treatment is required for activation of the n-type impurities introduced by the ion implantation process.
(1) It is extremely difficult to activate an impurity, e.g., silicon (Si), implanted in the n-type AlGaAs layer 3. PA0 (2) Damage is readily produced in the neighborhood of the heterojunction interleaved between the GaAs layer 2 and the n-type AlGaAs layer 3. PA0 (3) Provided the temperature of the heat treatment is restricted to 700.degree. C. to prevent the aforementioned heat damage from occurring, the Si implanted in the AlGaAs layer 3 is scarcely activated, and the activation rate of the Si implanted in GaAs layers 2 and 4 is decreased to approximately 60%. PA0 (4) A heat treatment causes damge to occur not only in the neighborhood of the heterojunction but also in the entire region of the layer configuration, and this damage can not be recovered by annealing.
The above description has clarified that a depletion type element produced by employing an ion implantation process has drawbacks including (1) a decrease in electron mobility particularly in the layer in which a two-dimensional electron gas is expected to accumulate; (2) greater resistivity in the source region and the drain region, in the regions connecting the source region and the region facing a gate electrode, and in the regions connecting the drain region and the region facing the gate electrode; and (3) greater power consumption.